Embodiments of the present disclosure relate to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device having a buried gate and a method for forming the same.
If the area occupied by unit cell is reduced, the number of unit cells per wafer increases, thereby improving productivity. Several methods for reducing the area of unit cell have been proposed. One method is to replace a conventional planar gate having a horizontal channel region with a recess gate. In the recess gate structure, a recess is formed in a substrate and a channel region is formed along a curved surface of the recess and a gate is formed in the recess. Furthermore, a buried gate has been studied which can reduce parasitic capacitance of a bit line by burying the entire gate within the recess.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device having a buried gate. Referring to FIG. 1, device isolation film 20 defining an active region 17 is formed in a semiconductor substrate 10, and a sidewall oxide film 15 is formed at a sidewall of the device isolation film 20.
A mask pattern 18 defining a buried gate is formed over the semiconductor substrate 10, and an etching process is performed using the mask pattern 18 as an etch mask, resulting in formation of a recess 27 in the semiconductor substrate 10.
A buried gate is formed to be buried in the recess 27. The buried gate includes: a recess 27 having a predetermined depth which is formed in the active region 17 or the device isolation film 20; a gate insulation film 35 formed with a thin thickness over the recess 27; and a gate conductive film 40 buried in the bottom of the recess 27 and having the gate insulation film 35. A sealing film 45 is formed over the gate conductive film 35, such that individual buried gates are isolated from each other. Junction regions 30 are formed in the active region 17 located at both sides of the buried gate, respectively.
If data “1” is stored in a cell of the above-mentioned semiconductor device, a leakage current occurs in the cell. Specifically, Gate Induced Drain Leakage (GIDL) and junction leakage occur as shown in FIG. 1. The leakage currents flow out through an external body electrode after passing through a P-well region of the active region 17. If a voltage (Vbody) of the body electrode is set to a low absolute value, leakage current decreases and retention characteristics improve.
However, GIDL, junction leakage, and an off leakage of a transistor may coexist in a cell. In this case, if the body electrode has a low voltage, retention characteristics of the cell having both GIDL and junction leakage may improve. However, the off leakage further increases in a cell in which the off leakage of the transistor occurs, resulting in deterioration of retention characteristics.